Ethernet Physical Design Engineer

Post Date: 02 Dec 09

Education:

BSEE with 2+ years of related experience, MSEE with 2+ years of related experience

Experience:

Own any part of the process from netlist handoff to tapeout:

Floor planning, power planning and signoff, place and route, timing closure, and physical verification

Verify effects of crosstalk and electromigration.

Support ASIC die size estimation studies and resource and schedule planning

Write scripts in Perl and TCL to achieve higher

Efficient with Perl and Tcl programming

DESCRIPTION OF FUNCTION & RESPONSIBILITY:

implement APR from netlist to gds

analyze and fix SI effect

analyze and meetIR-drop and EM requirements

perform ECO and metal spin

support die size estimation

SPECIAL REQUIREMENTS:

Efficient with Synopsys or Cadence place and route tools/flows

Location: Shanghai (China)

Please send full resume to Raymond.wu@atheros.com