Ethernet Digital Design Engineer

QUALIFICATION (DETAIL):

Education:

BS in Electrical/Electronics Engineering, MS preferred

Experience:

• 3 years experience with Verilog programming, logic synthesis and gate timing. A proven record of delivering successful ASIC's to the market is preferred.
• One or more advantages as following are highly desirable: A strong background in digital communication, signal processing and networking protocols; IC Design experiences in wireless communications and audio processing; Experiences with ARM/DSP, AHB bus and External interface development.
• Good communication skills in English.
• Experience in Bluetooth chip design a plus
• Must be proficient in RTL coding, logic synthesis, gate-level simulations.
• Good knowledge of IC design backend flows.
• Experiences in IC life-cycle from conception, design, verification, top-level netlist with pads to tape-out, chip-testing and mass-production.
• FPGA, PCB or embedded SW skill is a plus.

DESCRIPTION OF FUNCTION & RESPONSIBILITY:

The Digital Design Engineer will be responsible for designing our wireless and SOC ASIC's. You will work closely with our architecture/algorithm engineers to explore ideas for next generation products and then develop RTL to tern these ideas into customer solutions.

• Chip features specification and RTL design
• Synthesis, verification, timing.
• FPGA emulation, lab validation and debugging.

Location: Shanghai (China)

Please send full resume to Raymond.wu@atheros.com